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| 1. general description the IP4787CZ32 is designed to protect hi gh-definition multimedia interface (hdmi) receiver interfaces. it includes hdm i 5 v power management, data display channel (ddc) buffering and decoupling, hot plug drive, backdrive protection, consumer electronic control (cec) buffering and decoupling, and ? 8 kv contact electrostatic discharge (esd) protection for all i/os in accordance with the iec 61000-4-2, level 4 standard. the IP4787CZ32 incorporates transmission line clamping (tlc) technology on the high-speed transition-minimized differential si gnaling (tmds) lines to simplify routing and help reduce impedance discontinuities . all tmds lines are protected by an impedance-matched diode configuration that minimizes impedance discontinuities caused by typical shunt diodes. the 5 v power management enables host access to the (extended display identification data (edid)) memory even if no hdmi plug is connected. the overall load to the 5 v line is according to the hdmi requirements. the ddc lines use a buffering concept which de couples the internal capacitive load from the external capacitive load for use with standard complementary metal oxide semiconductor (cmos) or low voltage transistor-transistor logic (lvttl) i/o cells down to 1.2 v. this buffering also redrives the ddc and cec signals, allowing the use of longer or cheaper hdmi cables with a higher capacitance. the internal hot plug drive module simplifies the application of the hdmi receiver to control the hot plug signal. all lines provide appropriate integrated pu ll-ups and pull-downs fo r hdmi compliance and backdrive protection to guarantee that hdmi interface signals are not pulled down if the system is powered down or enters standby mode. only a single external capacitor is required for operation. 2. features and benefits ? hdmi 1.3a and 1.4, 340 mhz pixel clock, deep color and hdmi ethernet and audio return channel (heac) compatible ? pb-free, restriction of hazardous substanc es (rohs) compliant and free of halogen and antimony (dark green compliant) ? robust esd protection without degradation after repeated esd strikes ? impedance matched 100 ? differential transmission line esd protection for tmds lines ( ? 10 ? ). no printed-circuit board (pcb) pre-compensation required ? all external i/o lines with esd protection of at least ? 8 kv in accordance with the iec 61000-4-2, level 4 standard IP4787CZ32 dvi and hdmi interf ace esd protection, ddc/cec buffering, hot plug handling an d backdrive protection rev. 2 ? 20 december 2012 product data sheet hvqfn32
IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 2 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection ? ddc capacitive decoupling between syst em side and hdmi connector side and buffering to drive cable with high capacitive load (> 700 pf/25 m) ? hot plug drive module ? utility biasing module (heac compliant) ? cec buffering and isolation, with integrated backdrive-protected 26 k ? pull-up ? simplified flow-throu gh routing utilizing less overall pcb space ? highest integration in a small footprint, pcb level, optimized rf routing, 32-pin hvqfn leadless package 3. applications ? the IP4787CZ32 can be used for a wide rang e of hdmi sink devi ces, consumer and computing electronics: ? digital high-definition (hd) tv ? set-top box ? pc monitor ? projector ? multimedia audio amplifier ? hdmi picture performance quality enhancer module ? digital visual interface (dvi) 4. ordering information table 1. ordering information type number package name description version IP4787CZ32 hvqfn32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 ? 5 ? 0.85 mm sot617-3 IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 3 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 5. functional diagram fig 1. functional diagram IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 4 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration IP4787CZ32 ! " #$ %& #'! %' ' #$ %& ( )*) + , + + ' + " +,$ + - . . - / 0 ! 1 2 2 1 0 2 1 ! / 2 2 2 0 - . / ! 3 4 56 table 2. pin description pin name description 1 tmds_d2+_sys tmds to asic inside system 2tmds_d2 ? _sys tmds to asic inside system 3 tmds_d1+_sys tmds to asic inside system 4tmds_d1 ? _sys tmds to asic inside system 5 tmds_d0+_sys tmds to asic inside system 6tmds_d0 ? _sys tmds to asic inside system 7 tmds_ck+_sys tmds to asic inside system 8tmds_ck ? _sys tmds to asic inside system 9 ddc_clk_sys ddc clock system side 10 ddc_dat_sys ddc data system side 11 v cc(5v0) 5 v supply input 12 hotplug_con hot plug output to connector 13 hdmi_5v0_con 5 v input from connector 14 ddc_dat_con ddc data connector side IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 5 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 7. limiting values [1] connector-side pins (typically d enoted with ?_con? suffix) to ground. [2] system-side pins: cec_sys, ddc_dat_sys, ddc_clk_sys, hotplug_ctrl, active, v cc(sys) and v cc(5v0) . 15 ddc_clk_con ddc clock connector side 16 utility_con utility line esd protection 17 tmds_ck ? _con tmds esd protection to connector 18 tmds_ck+_con tmds esd protection to connector 19 tmds_d0 ? _con tmds esd protection to connector 20 tmds_d0+_con tmds esd protection to connector 21 tmds_d1 ? _con tmds esd protection to connector 22 tmds_d1+_con tmds esd protection to connector 23 tmds_d2 ? _con tmds esd protection to connector 24 tmds_d2+_con tmds esd protection to connector 25 cec_con cec signal connector side 26 esd_bypass esd bias voltage 27 v cc(sys) supply voltage for level shifting 28 active cec standby mode control (low for lowest power, cec-only mode) 29 cec_sys cec i/o signal system side 30 enable_ldo 5 v ldo enable 31 n.c. not connected 32 hotplug_ctrl hot plug control input from system side ground pad gnd ground table 2. pin description ?continued pin name description table 3. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v cc(5v0) supply voltage (5.0 v) gnd ? 0.5 6.5 v v i input voltage i/o pins gnd ? 0.5 5.5 v v esd electrostatic discharge voltage iec 61000-4-2, level 4 (contact) [1] - ? 8kv iec 61000-4-2, level 1 (contact) [2] - ? 2kv p tot total power dissipation ddc operating at 100 khz; cec operating at 1 khz; 50 % duty cycle; active = high -50mw ddc and cec bus in idle mode; active = high -3.0mw ddc and cec bus in idle mode; active = low -1 . 2m w t amb ambient temperature ? 25 +85 ?c t stg storage temperature ? 55 +125 ?c IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 6 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 8. static characteristics [1] hdmi_5v0_con is used as supply in case enable_ldo is inactive and v cc(5v0) is unavailable or lower than hdmi_5v0_con. [1] this parameter is guaranteed by design. [2] capacitive dip at hdmi time domain reflectometer (tdr) measurement conditions. [3] ansi-esd sp5.5.1-2004, esd sensitivity testing transmission line pulse (tlp) component level method 50 tdr. [4] signal pins: tmds_d0+_con, tmds_d0 ? _con, tmds_d1+_con, tmds_d1 ? _con, tmds_d2+_con, tmds_d2 ? _con, tmds_ck+_con, tmds_ck ?_con, tmds_d0+_sys, tmds_d0 ? _sys, tmds_d1+_sys, tmds_d1 ? _sys, tmds_d2+_sys, tmds_d2 ? _sys, tmds_ck+_sys and tmds_ck ?_sys. [5] backdrive current from tmds_x_sys and tmds_x_con pins to local v cc(5v0) bias rail at power-down. device does not block backdrive current leakage through the device to/fr om asic i/o pins connected to tmds_x_sys pins. table 4. supplies t amb = ? 25 ? c to +85 ? c unless otherwise specified. symbol parameter conditions min typ max unit v cc(5v0) supply voltage (5.0 v) 4.5 5.0 6.5 v v (hdmi_5v0_con) voltage on pin hdmi_5v0_con [1] 4.5 5.0 6.5 v v cc(sys) system supply voltage 1.1 3.3 3.63 v table 5. tmds protection circuit t amb = ? 25 ? c to +85 ? c unless otherwise specified. symbol parameter conditions min typ max unit tmds channel z i(dif) differential input impedance tdr measured; t r = 200 ps 90 100 110 ? c eff effective capacitance equivalent shunt capacitance for tdr minimum; t r =200ps [1] [2] -0.6-pf protection diode v brzd zener diode breakdown voltage i = 1.0 ma 6.0 - 9.0 v r dyn dynamic resistance surge; i = 1.0 a; iec 61000-4-5/9 positive transient - 1.0 - ? negative transient - 1.0 - ? tlp [3] positive transient - 1.0 - ? negative transient - 1.0 - ? i bck back current v cc(5v0) IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 9 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection [1] the device is active if the input volt age at pin active is above the high level. [2] this parameter is guaranteed by design. [3] capacitive load measured at power-on. [4] no external pull-up resistor attached. [5] see section 11.7 for details on the hot plug functionality. [1] the active pin should be connected permanently to v cc(5v0) or v cc(sys) if no enable control is needed. [2] ddc buffers, hot plug detect (hpd) driver, utili ty bias and hdmi_5v0_con out enabled; cec buffer enabled. [3] ddc buffers, hpd driver, utility bias and hdmi_5v0_con out disabled; cec buffer enabled. [4] this parameter is guaranteed by design. hotplug_con; utility_con [1] v oh high-level output voltage 3.6 4 4.4 v v ol low-level output voltage - - 0.4 v r o output resistance 0.8 1.0 1.2 k ? c o output capacitance v cc(5v0) =0v; v cc(sys) =0v; v bias =2.5v; ac input = 3.5 v (p-p) ; f=100khz [2] -8 . 01 0p f hotplug_ctrl [1] v ih high-level input voltage high = hot plug on [5] 1.0 - - v v il low-level input voltage low = hot plug off [5] --0 . 4v r pd pull-down resistance 60 100 140 k ? c i input capacitance v cc(5v0) =0v; v cc(sys) =0v; v bias =2.5v; ac input = 3.5 v (p-p) ; f=100khz [2] -6 . 07 . 0p f table 7. static characteristics ?continued t amb = ? 25 ? c to +85 ? c unless otherwise specified. symbol parameter conditions min typ max unit table 8. power management v cc(sys) = 1.10 v to 3.63 v; v cc(5v0) = 4.5 v to 6.5 v; gnd = 0 v; t amb = ? 25 ? c to +85 ? c unless otherwise specified. symbol parameter conditions min typ max unit system side: input pin active [1] v ih high-level input voltage high = active [2] 1.0--v v il low-level input voltage low = standby [3] --0.4v r pd pull-down resistance 680 k ? c i input capacitance v i =3v or 0v [4] - 67pf system side: input pin enable_ldo v ih high-level input voltage 1.0 - - v v il low-level input voltage - - 0.4 v r pu pull-up resistance 680 k ? c i input capacitance v i =3v or 0v [4] - 67pf IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 10 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 9. dynamic characteristics [1] all dynamic measurements are done with a 75 pf load. rise ti mes on system side are determined only by internal pull-up resist ors. rise times on connector side are determined by external 1.5 k ? and internal pull-up resistors. table 9. dynamic characteristics v cc(5v0) =5.0v; v cc(sys) = 1.8 v; gnd = 0 v; t amb = ? 25 ? c to +85 ? c unless otherwise specified. symbol parameter conditions min typ max unit ddc_dat_sys, ddc_clk_sys, ddc_dat_con, ddc_clk_con [1] t plh low to high propagation delay system side to connector side figure 15 -80-ns t phl high to low propagation delay system side to connector side figure 15 -60-ns t plh low to high propagat ion delay connector si de to system side figure 16 -120-ns t phl high to low propagation delay c onnector side to system side figure 16 -80-ns t tlh low to high transition time connector side figure 17 -150-ns t thl high to low transition time connector side figure 17 -100-ns t tlh low to high transition time system side figure 18 -250-ns t thl high to low transition time system side figure 18 -80-ns t r = 200 ps; no filter; v cc(5v0) =5v 100 ? differential (ch1 + ch2) fig 3. differential tdr plot ) ) )2 )1 )! )/ - 0 3 " 7 5 8 9" IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 11 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection (1) sdd21 (2) scc21 normalized to 100 ? ; differential pairs at signal pins. fig 4. mixed-mode differential and commo n-mode insertion loss; typical values (1) sdd21; near end crosstalk (next) (2) sdd21; far end crosstalk (fext) normalized to 100 ? ; differential pairs ch1/ch2 versus ch3/ch4 fig 5. mixed-mode differential and common-mode next / fext; typical values 018aaa086 f (hz) 10 6 10 10 10 9 10 7 10 8 C9 C3 3 sdd21; scc21 (db) C15 (1) (2) 018aaa087 f (hz) 10 6 10 10 10 9 10 7 10 8 C9 C3 3 sdd21 (db) C15 (1) (2) IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 12 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 227 mhz pixel clock horizontal scale: 200 mv/div vertical scale: 90 ps/div offset: 42.6 mv fig 6. eye diagram using IP4787CZ32 (1080p, 12 bit) 297 mhz pixel clock horizontal scale: 200 mv/div vertical scale: 67.5 ps/div offset: 42.6 mv fig 7. eye diagram using IP4787CZ32 (1080p, 16 bit) IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 13 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection deviation from typical capacitance normalized at v bias =2.5v fig 8. line capacitance as a function of bias voltage; typical values iec 61000-4-5; t p =8/20 ? s; positive pulse iec 61000-4-5; t p =8/20 ? s; negative pulse fig 9. dynamic resistance with positive clamping fig 10. dynamic resistance with negative clamping v bias (v) C1.0 7.0 5.0 1.0 3.0 018aaa090 0.0 C0.2 0.2 0.4 c line (pf) C0.4 i (a) 1.2 1.0 0.6 1.1 0.9 0.7 0.5 0.8 018aaa091 3.50 3.25 3.75 4.00 v cl (v) 3.00 i (a) 0.4 1.2 1.0 0.6 0.8 018aaa092 1.5 2.0 2.5 v cl (v) 1.0 IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 14 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection t p = 100 ns; tlp; signal pins; typical values t p = 100 ns; tlp; signal pins; typical values fig 11. dynamic resistance with positive clampi ng fig 12. dynamic resistance with negative clamping (1) 5.3 v; maximum values; hdmi cts tid 7-11 (2) 4.8 v; minimum values; hdmi cts tid 7-11 (3) i = 0 ma (4) i = 55 ma (5) v cc(5v0) supply input; 4.925 v to 6.5 v (1) v cc(5v0) =4.5v (2) v cc(5v0) =5.0v (3) v cc(5v0) =5.5v (4) v cc(5v0) =6.5v fig 13. overvoltage limiter function (hdmi_5v0_con) fig 14. overcurrent limiter function (hdmi_5v0_con) v cl (v) 622 18 10 14 018aaa093 8 10 6 4 2 12 14 i (a) 0 v cl (v) C12 0 C4 C8 018aaa094 0 i (a) C14 C12 C10 C8 C6 C4 C2 018aaa095 v cc(5v0) (v) 5.0 6.5 6.0 5.5 5.5 5.0 6.0 6.5 v i (v) 4.5 (1) (5) (4) (3) (2) i o (a) 0.00 0.04 0.08 0.12 0.14 0.10 0.06 0.02 018aaa096 2.0 4.0 6.0 v o (v) 0.0 (1) (4) (3) (2) IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 15 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 10. ac waveforms 10.1 ddc propagation delay fig 15. propagation delay ddc, ddc sys tem side to ddc connector side fig 16. propagation delay ddc, ddc co nnector side to ddc system side : 3 5 * * 5 " )! '! " ' " " " )! '! " $# $ # )! " '! " : 3 5 * * 5 " )! '! " ' " " )! '! " $# $ # )! " )! " '! " IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 16 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 10.2 ddc transition time fig 17. transition ti me ddc connector side fig 18. transition time ddc system side : 3 5 * * 5 ' " '! - ; '! " ; '! " " " $# $ # : 3 5 * * 5 " - ; " ; " ' " " $# $ # '! IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 17 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 11. application information 11.1 hdmi connector side esd protection all pins directly interfacing with the hdmi connector provide up to 8 kv contact esd protection according to iec 610 00-4-2, level 4. in order to utilize the full sc ope of this protection it is recommended to connect all connector side pins to the hdmi connector. 11.2 tmds esd protection concept to protect the tmds lines and also to comp ly with the impedance requirements of the hdmi specification, the IP4787CZ32 pr ovides esd protection with matched tlc esd structures. typical dual rail clamp (drc) or rail-to-rail shunt structures are common for low-capacitance esd protection ( figure 19 ; left side) where the dominant factor for the tmds line impedance dip is det ermined by the capacitive load to ground. parasitic lead inductances of the packaging in this case work against the esd clamping performance by including the ? i/? t reactance of the inductance into the path of the esd shunt. the IP4787CZ32 utilizes these inhe rent inductances in series with the transmission line in order to present an effective capacitive load of roughly only 0.7 pf. this tlc structure minimizes the capacitive dip, for ideal signal integrity ( figure 19 ; right side) without complicated pcb pre-compensation. as a be neficial side effect, this enhances the esd performance of the device as well, sinc e the reactance of the series inductance attenuates the fast initial peak of the esd pul se for a lower residual pulse delivered to the application specific in tegrated circuit (asic). a. classic parallel esd shunt protection b. improved series shunt tlc clamping fig 19. tlc esd protection of tmds lines 018aaa101 018aaa102 IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 18 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 11.3 operating and standby modes the operating mode of ip 4787cz32 depends on th e availability of the v cc(5v0) and v cc(sys) supply voltages and on the state of th e active input signal. without availability of both supplies, IP4787CZ32 is in standby mode. as soon as v cc(5v0) and v cc(sys) are within the range specified in section 8 , the part is in an operating mode that can be controlled via the active input signal. in case active is low, only the cec buffer is active and enabled to receive or send cec commands. all other outputs are in a high-ohmic state. a high input signal enables all parts of IP4787CZ32 and puts the device into full operating mode. [1] x = do not care; l = low-level input; h = high-level input if no cec standby mode is required, or if no special power-down modes are desired, the active pin can be pulled high to v cc(5v0) or v cc(sys) for continuous hdmi and cec operation as soon as the supplies are aviailable. strapping the active = v cc(sys) =v dd of asic guarantees that all interface signals ending with the suffix ?_sys? on th e system side are disabled when v cc(sys) goes low, protecting the asic i/o signal s from exceedin g its local v dd . in this mode, even if v cc(5v0) is powered, hdmi_5v0_con goes active and hot plug events can be detected only when the asic power supply rail is on. strapping active = v cc(5v0) is the most basic configuration where the buffers are enabled whenever the local v cc(5v0) and v cc(sys) supplies reach minimum operating levels. table 10. IP4787CZ32 operating modes v cc(sys) v cc(5v0) active [1] mode description < 1.1 v < 4.5 v x standby mode all outputs high-ohmic ? 1.1 v ? 4.5 v l cec standby mode cec circuit active; all other outputs high-ohmic h full operating mode all functional blocks active IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 19 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 11.4 ddc circuit the ddc bus circuit integrates all required pull-ups, and provides full capacitive decoupling between the hdmi connector and the ddc bus lines on the pcb. the capacitive decoupling ensures that the maximu m capacitive load is well within the 50 pf maximum of the hdmi specific ation. no external pull-ups or pull-downs are required. the bidirectional buffers support high-capacit ive load on the hdmi cable-side. various non-compliant but prevalent low-cost cables ha ve been observed with a capacitive load of up to 6 nf on the ddc lines, far exceeding the 700 pf hdmi limit. the IP4787CZ32 can easily decouple this from the weaker as ic i/o buffers, and drive the rogue cable successfully. a. ddc clock b. ddc data fig 20. ddc circuit 1. <9 2)/! <9 +,$ '! ' " 1. <9 2)/! <9 +,$ '! ' " (1) valid i 2 c signaling example on the cable (c onnector side) from 5 v (high) to approximately 1 v (low). (2) valid logic-level signaling example to the asic (system side) from 1.8 v (high) to approximately 0.5 v (low). fig 21. ddc level shifting waveform example 5 4 3 2 1 0 time v (1) (2) aaa IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 20 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 11.5 cec circuit the logical multidrop topology of the cec bus can include complex physical stubs, loading cables, and interconnects that may deteriorate signal quality. the IP4787CZ32 includes a full bidirectional buffer to drive the cec bus and isolate the cec microcontroller or asic ge neral-purpose input/output (gpio). the cec buffer derives power from an on-board 3.3 v regulator from the 5 v power domain (see figure 22 ). this allows extensive system power management configurations and guarantees an hdmi-compliant v (cec_con) on the connector, as well as a backdrive-protected 125 ? a nominal cec pull-up which does not degrade the bus when powered down. by placing the cec microcontroller and either v cc(5v0) or hdmi_5v_con input on a 5 v rail as shown in figure 27 , the cec microcontroller can communicate over cec for power commands, and then enable the hdmi port via the active pin, as well as the rest of the system as needed. fig 22. cec module '! <9 / <9 +,$ + + ' " 2 2 IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 21 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 11.6 logic low i 2 c voltage shifter the ddc buffers provide an additional feat ure commonly required for high-integration hdmi asics which are limited to cmos or lvttl low-leve l input voltage (v il ) on their available i/o buffer cells. these i/os are not strictly compliant with the 0.3 v dd threshold voltage levels of i 2 c and may miss intended logic low levels on the cable between 0.8 v and 1.5 v (typical values). this feature is also included in the cec buffer thus allowing standard i/o buffer cells to be used in asics and microcontr ollers connected to cec_sys. (1) v ol_cec(max) maximum output voltage driven to system (asic) side when cec is logic low (2) v ol_ddc(max) maximum output voltage driven to system (asic) side when ddc is logic low (3) v il(max) maximum input voltage on system (asic) side to drive ddc or cec logic low (4) v ih(min) minimum input voltage on system (asic) side to drive ddc or cec logic high fig 23. logic voltage thresholds as a function of supply voltage; on connector (hdmi) side )! )! 2 2)! 1 ) )2 )1 )! )/ ). )- " " " " 1" 2" IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 22 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 11.7 hot plug circuit the IP4787CZ32 includes a hot plug drive circuit that simplifies the hot plug application. it drives an hdmi-compliant hot plug signal to the hdmi sink. by design, the hot plug drive circuit avoids glitches or short pulses on the hot plug line and is protected against shortage to the 5 v input. in order to signal a high level on the hotplug_con output pin, the hotplug_ctrl input pin needs to be driven high and a 5 v supply needs to be available on hdmi_5v0_con. driving hotplug_ctrl lo w generates a low-level output on the hotplug_con pin. an integrated 100 k ? resistor on the hotplug_ctrl pin prevents from undefined (floating) state on hotplug_con. in full accordance with the hdmi specific ation, the low and high output levels generated on the hotplug_con output always show a proper impedance of 1 k ? . 11.8 heac support and utility pin in addition to the esd protection impl emented at utility_con, IP4787CZ32 also includes a biasing output for heac functionality. this output buffer is closely tied to the output on the hotplug_con pin. a low-le vel output signal on hotplug_con also causes a low output on utility_con and a high level on hotplug_con results in an identical high output on utility_con. as for hotplug_con, the low and hi gh output levels generated on the utility_con output always show an impedance of 1 k ? . fig 24. hot plug circuit <9 <9 +,$ #$ %& #$ %&( #'! ( , fig 25. utility circuit <9 +,$ %' ' #'! <9 #$ %&( ( , IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 23 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 11.9 edid programming using enable_ldo IP4787CZ32 has a special mode providing an in ternal 5 v supply to the connector side power supply. this special mode allows programming of an extended display identification data programmable read-only memory (edid prom) placed on ddc bus between the device and the hdmi connector. the edid programming mode can be utilized by driving an active high signal to the enable_ldo input pin. this enables an internal 5 v low dropout (ldo) to provide the supply on v cc(5v0) to hdmi_5v0_con pin in case no higher supply is available at this pin. an active low input to enable_ldo di sables the edid programming mode. 11.10 backdrive protection the hdmi connector contains various signals which can partly supply current into an hdmi device that is powered down. typically, the ddc lines and the cec signals ca n force significant cu rrent back into the powered-down rails as shown in figure 26 , causing power-on rese t problems with the system, and possible damage. the IP4787CZ32 prevents this backdrive condition whenever the i/o voltage is greater than the local supply. fig 26. generalized backdrive protection 018aaa109 hdmi asic hdmi source supply off 5 v backdrive current i 2 c-bus asic hdmi sink IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 24 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 11.11 schematic view of application only a single external component (c o =1 ? f) is required to protect and interface the asic to a complete and compliant hdmi por t. the 100 nf esd bypass capacitor is optional. fig 27. schematic view of IP4787CZ32 application = ' + + - 0 / 1 2 0 - . ! ! / 2 1 $ 1 ! / . - 0 2 2 . %' ' + #$ %& #'! #$ %&( ) 2)/2 %$$ 1)! /)! %$$ => > + ?: 4" 2 + , + IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 25 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 11.12 typical application the IP4787CZ32 is designed to simplify routing to the hdmi connector, and ease the incorporation of high-level esd protec tion into delicately balanced high-speed tmds lines. these lines rely on ti ghtly controlled microstrip or stripline transmission lines with minimal impedance discontinuities, which can deteriorate return loss, increase deterministic jitter and generally erode overall link signal integrity. normally, when designing a pcb with standard shunt esd clamps, careful consideration must be given to manual pre-compensat ion of the additional load of the added esd component. with the IP4787CZ32 tlcs, the esd suppressor is designed to maintain the characteristic impedance of the pcb microstrip or stripline. therefore the designer has to be concerned only with the standard-controlled impedance of the unloaded pcb lines. this simplifies the task of the pcb designer, and minimizes the tuning cycles, which are sometimes required when pre-compensation misses the mark. a basic application diagram for the esd protection of an hdmi interface is shown in figure 28 for a type-a hdmi connector. the optimized hvqfn32 pinning simplifies the pcb design to keep the esd protection close to the connector where it can minimi ze the coupling of the esd pulse onto other lines in the system during a strike. due to the integrated pull-up and pull-down resistors, only two external capacitors are required to implement a fully compliant hdmi port. fig 28. application of the IP4787CZ32 showing optimized hdmi type-a connector routing 33 IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 26 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 12. package outline fig 29. package outline sot617-3 (hvqfn32) references outline version european projection issue date iec jedec jeita sot617-3 mo-220 sot617-3_po 11-06-14 11-06-21 unit (1) mm max nom min 0.85 0.05 0.00 0.2 5.1 4.9 3.75 3.45 5.1 4.9 3.75 3.45 0.5 3.5 a 1 dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm sot617-3 bc 0.30 0.18 d (1) a (1) d h e (1) e h ee 1 e 2 l 3.5 vw 0.1 0.1 y 0.05 0.5 0.3 y 1 0.05 0 2.5 5 mm scale 1/2 e ac b v c w terminal 1 index area a a 1 detail x y y 1 c e l e h d h e e 1 b 916 32 25 24 17 8 1 x d e c b a e 2 terminal 1 index area 1/2 e IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 27 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 13. soldering fig 30. footprint recommendation sot617-3 (hvqfn32) sot617-3 footprint information for reflow soldering of hvqfn32 package dimensions in mm ax ay bx by d slx sly spx tot spy tot spx spy gx gy hx hy 6.000 6.000 4.200 4.200 p 0.500 0.290 c 0.900 3.500 3.500 2.100 2.100 0.500 0.500 5.300 5.300 6.250 6.250 nspx nspy 33 sot617-3_fr occupied area ax bx slx gx gy hy hx aybysly p 0.025 0.025 d (0.105) spx tot spy tot nspx nspy spx spy solder land plus solder paste solder land solder paste deposit c generic footprint pattern refer to the package outline drawing for actual layout issue date 07-05-07 09-06-15 IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 28 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 14. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 14.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 14.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 29 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 14.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 31 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 11 and 12 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 31 . table 11. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 12. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 30 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 15. glossary hdmi sink ? device which receives hdmi signals for example, a tv set. hdmi source ? device which transmits hdmi si gnal for example, dvd player. msl: moisture sensitivity level fig 31. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 31 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 16. revision history table 13. revision history document id release date data sheet status change notice supersedes IP4787CZ32 v.2 20121220 product data sheet - IP4787CZ32 v.1 modifications: ? changed data sheet status to ?product data sheet? IP4787CZ32 v.1 20120730 preliminary data sheet - - IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 32 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. IP4787CZ32 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 20 december 2012 33 of 34 nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. quick reference data ? the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not comple te, exhaustive or legally binding. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors IP4787CZ32 dvi and hdmi interface esd and overcurrent protection ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 20 december 2012 document identifier: IP4787CZ32 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 9 dynamic characteristics . . . . . . . . . . . . . . . . . 10 10 ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 15 10.1 ddc propagation delay . . . . . . . . . . . . . . . . . 15 10.2 ddc transition time . . . . . . . . . . . . . . . . . . . . 16 11 application information. . . . . . . . . . . . . . . . . . 17 11.1 hdmi connector side esd protection . . . . . . . 17 11.2 tmds esd protection concept. . . . . . . . . . . . 17 11.3 operating and standby modes . . . . . . . . . . . . 18 11.4 ddc circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11.5 cec circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.6 logic low i 2 c voltage shifter . . . . . . . . . . . . . . 21 11.7 hot plug circuit . . . . . . . . . . . . . . . . . . . . . . . . 22 11.8 heac support and utility pin. . . . . . . . . . . . . . 22 11.9 edid programming using enable_ldo. . . . 23 11.10 backdrive protection . . . . . . . . . . . . . . . . . . . . 23 11.11 schematic view of application . . . . . . . . . . . . 24 11.12 typical application . . . . . . . . . . . . . . . . . . . . . 25 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 26 13 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14 soldering of smd packages . . . . . . . . . . . . . . 28 14.1 introduction to soldering . . . . . . . . . . . . . . . . . 28 14.2 wave and reflow soldering . . . . . . . . . . . . . . . 28 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 28 14.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 29 15 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 31 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 32 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 32 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 17.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 33 18 contact information. . . . . . . . . . . . . . . . . . . . . 33 19 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 |
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